1. Field of the Invention
The present invention relates to technology for realizing a processor that has low power consumption and uses a pipeline processing system.
2. Description of the Related Art
Generally, a pipeline processing system is used in order to enhance the processing performance of a processor. In a processor using a pipeline processing system, when a source operand value necessary for execution of an instruction is to be acquired, if the newest source operand value exists in a pipeline, that value existing in the pipeline is acquired, rather than a value that exists in a register file. This is called “operand forwarding” or “operand bypassing”. In this way, before a calculated value obtained in accordance with a preceding instruction is written in the register file, a next instruction can be executed using the newly calculated value.
It is not necessary to read out a value from the register file when operand forwarding is performed. Further, if it is known that a calculated value is operand-forwarded, and does not need to be read out after that, it is not necessary to write that calculated value in the register file. It is possible to reduce the power consumption of a processor by reducing reading/writing of a value from/to the register file.
According to a method disclosed in Non-Patent Document 1 (“Reducing Power Consumption of Register Files through Operand Reuse”, Information Processing Society of Japan Research Report, Computer Architecture Research Group Report 2002(81), Aug. 22, 2002: pp. 13-18), a case is detected in which a destination register for a preceding instruction and a source operand register and a destination register for a succeeding instruction match. In this case, a calculated value obtained in accordance with the preceding instruction is operand-forwarded to the succeeding instruction. Moreover, a register value is updated in accordance with the succeeding instruction, and thus the calculated value obtained in accordance with the preceding instruction will not be read out after that. Specifically, the succeeding instruction designates that the calculated value obtained in accordance with the preceding instruction will no longer be read out. Accordingly, the calculated value obtained in accordance with the preceding instruction does not need to be stored in the register file.
According to a method in Patent Document 1 (International Publication WO 2007/083421), when a calculated value obtained in accordance with a preceding instruction is operand-forwarded, it is defined in the preceding instruction whether or not that calculated value obtained in accordance with the preceding instruction is stored in a register file. Specifically, the preceding instruction designates that the calculated value obtained in accordance with that instruction will no longer be read out after operand forwarding.
According to the method in Non-Patent Document 1, if a succeeding instruction designates both a destination register and a source operand register, it can be designated that a calculated value obtained in accordance with a preceding instruction will no longer be read out. Accordingly, if the succeeding instruction is an instruction that does not designate a destination register, such as a compare instruction, a store instruction to a memory, or a branch instruction, it cannot be designated that a calculated value obtained in accordance with the preceding instruction will no longer be read out.
If a calculated value obtained in accordance with a preceding instruction is operand-forwarded to two or more succeeding instructions, it is not possible to omit the storing of that calculated value in a register file unless it is confirmed that the last operand forwarding has succeeded. However, a method of enabling this is not disclosed in International Publication WO 2007/083421. Further, in the method in International Publication WO 2007/083421, whether or not the writing to a register file is necessary is indicated in each preceding instruction. Thus, according to the method in International Publication WO 2007/083421, an average instruction bit length and the program size are increased, and power consumption is also increased.